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CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 72-mbit (2 m 36/4 m 18/1 m 72) pipelined sram with nobl? architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-15032 rev. *i revised may 17, 2011 72-mbit (2 m 36/4 m 18/1 m 72) pipelined sram with nobl? architecture features pin-compatible and functionally equivalent to zbt? supports 250 mhz bus operations with zero wait states ? available speed grades are 250, 200, and 167 mhz internally self-timed output buffe r control to eliminate the need to use asynchronous oe fully registered (inputs and outputs) for pipelined operation byte write capability single 2.5 v power supply 2.5 v io supply (v ddq ) fast clock-to-output times ? 3.0 ns (for 250-mhz device) clock enable (cen ) pin to suspend operation synchronous self-timed writes CY7C1470BV25, cy7c1472bv25 available in jedec-standard pb-free 100-pin tqfp, pb-free and non-pb-free 165-ball fbga package. cy7c1474bv25 available in pb-free and non-pb-free 209-ball fbga package ieee 1149.1 jtag bound ary scan compatible burst capability?linear or interleaved burst order ?zz? sleep mode option and stop clock option functional description the CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 are 2.5 v, 2 m 36/4 m 18/1 m 72 synchronous pipelined burst srams with no bus latency? (nobl ?? logic, respectively. they are designed to support unlimited true back-to-back read or write operations with no wait states. the CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 are equipped with the advanced (nobl) logic required to enable consecutive read or write operatio ns with data being transferred on every clock cycle. this feat ure dramatically improves the throughput of data in systems t hat require frequent read or write transitions. the CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 are pin-compatible and functionally equivalent to zbt devices. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation an d extends the previous clock cycle. write operations are controlled by the byte write selects (bw a ?bw d for CY7C1470BV25, bw a ?bw b for cy7c1472bv25, and bw a ?bw h for cy7c1474bv25) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state c ontrol. to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. selection guide description 250 mhz 200 mhz 167 mhz unit maximum access time 3.0 3.0 3.4 ns maximum operating current 450 450 400 ma maximum cmos standby current 120 120 120 ma [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 2 of 29 logic block diagram ? CY7C1470BV25 (2 m 36) logic block diagram ? cy7c1472bv25 (4 m 18) a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dq s dq p a dq p b dq p c dq p d d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s e c lk c en write drivers bw c bw d zz sleep control o u t p u t r e g i s t e r s a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dq s dq p a dq p b d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e c lk c en write drivers zz sleep control [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 3 of 29 logic block diagram ? cy7c1474bv25 (1 m 72) a0, a1, a c mode ce1 ce2 ce3 oe read logic dq s dq p a dq p b dq p c dq p d dq p e dq p f dq p g dq p h d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e c lk c en write drivers bw a bw b we zz sleep control bw c write registry and data coherency control logic bw d bw e bw f bw g bw h [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 4 of 29 contents pin configurations ........................................................... 5 pin definitions .................................................................. 7 functional overview ........................................................ 8 single read accesses ................................................ 8 burst read accesses .................................................. 8 single write accesses ................................................. 8 burst write accesses .................................................. 9 sleep mode ................................................................. 9 linear burst address table (mode = gnd) .................. 9 interleaved burst address table (mode = floating or vdd) ............................................... 9 zz mode electrical characteris tics ................................. 9 truth table ...................................................................... 10 partial write cycle description ..................................... 11 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 12 disabling the jtag feature ...................................... 12 tap controller state diagram ....................................... 12 test access port (tap) ............................................. 12 tap controller block diagram ...................................... 12 performing a tap reset ......................................... 12 tap registers ........................................................... 12 tap instruction set ................................................... 13 tap timing ...................................................................... 14 tap ac switching characteristics ............................... 15 2.5 v tap ac test conditions ....................................... 16 2.5 v tap ac output load equivalent ......................... 16 tap dc electrical characteristics and operating conditions ..................................................... 16 identification register definitions ................................ 16 scan register sizes ....................................................... 16 identification codes ....................................................... 17 boundary scan exit order (2 m 36) ........................... 17 boundary scan exit order (4 m 18) ........................... 18 boundary scan exit order (1 m 72) ........................... 18 maximum ratings ........................................................... 19 operating range ............................................................. 19 electrical characteristics ............................................... 19 capacitance .................................................................... 20 thermal resistance ........................................................ 20 ac test loads and waveforms ..................................... 20 switching characteristics .............................................. 21 switching waveforms .................................................... 22 ordering information ...................................................... 24 ordering code definitions ..... .................................... 24 package diagrams .......................................................... 25 acronyms ........................................................................ 27 document conventions ................................................. 27 units of measure ....................................................... 27 document history page ................................................. 28 sales, solutions, and legal information ...................... 29 worldwide sales and design s upport ......... .............. 29 products .................................................................... 29 psoc solutions ......................................................... 29 [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 5 of 29 pin configurations a a a a a 1 a 0 v ss v dd a a a a a a v ddq v ss dqb dqb dqb v ss v ddq dqb dqb v ss nc v dd dqa dqa v ddq v ss dqa dqa v ss v ddq v ddq v ss dqc dqc v ss v ddq dqc v dd v ss dqd dqd v ddq v ss dqd dqd dqd v ss v ddq a a ce 1 ce 2 bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz CY7C1470BV25 a a a a a 1 a 0 v ss v dd a a a a a a a nc nc v ddq v ss nc dqpa dqa dqa v ss v ddq dqa dqa v ss nc v dd dqa dqa v ddq v ss dqa dqa nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dqb dqb v ss v ddq dqb dqb v dd v ss dqb dqb v ddq v ss dqb dqb dqpb nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode cy7c1472bv25 bw d mode bw c dqc dqc dqc dqc dqpc dqd dqd dqd dqpb dqb dqa dqa dqa dqa dqpa dqb dqb (2 m 36) (4 m 18) bw b nc nc nc dqc nc nc(288) nc(144) nc(288) nc(144) dqpd a a a a a a figure 1. 100-pin tqfp pinout [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 6 of 29 pin configurations (continued) 165-ball fbga (15 17 1.4 mm) pinout CY7C1470BV25 (2 m 36) cy7c1472bv25 (4 m 18) 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g dqp c dq c dqp d nc dq d a ce 1 bw b ce 3 bw c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a v ddq bw d bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld nc oe a a nc v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g nc nc dqp b nc dq b a ce 1 ce 3 bw b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc a v ddq bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld a oe a a nc v ss v ddq nc dqpa v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a nc nc [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 7 of 29 pin definitions pin name io type pin description a0 a1 a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. bw a bw b bw c bw d bw e bw f bw g bw h input- synchronous byte write select inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bw a controls dq a and dqp a , bw b controls dq b and dqp b , bw c controls dq c and dqp c , bw d controls dq d and dqp d , bw e controls dq e and dqp e, bw f controls dq f and dqp f, bw g controls dq g and dqp g, bw h controls dq h and dqp h . we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input used to advance the on-chip address counter or load a new address . when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld must be driven low to load a new address. clk input- clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, active low . combined with the synchronous logic block inside the device to control the direction of the io pins. when low, the io pins can behave as outputs. when deasserted high, io pins are tri-stated, an d act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging fr om a deselected state and when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. dq s io- synchronous bidirectional data io lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [18:0] during the previous clock rise of the read cycl e. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq a ?dq h are placed in a tri-state condition. th e outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emergi ng from a deselected state, and when the device is deselected, regardless of the state of oe . dqp x io- synchronous bidirectional data parity io lines . functionally, these signals are identical to dq [71:0] . during write sequences, dqp a is controlled by bw a , dqp b is controlled by bw b , dqp c is controlled by bw c , and dqp d is controlled by bw d , dqp e is controlled by bw e, dqp f is controlled by bw f, dqp g is controlled by bw g, dqp h is controlled by bw h . mode input strap pin mode input . selects the burst order of the device. ti ed high selects the interleaved burst order. pulled low selects the linear burst order. mode must not change states during operation. when left floating mode defaults high, to an interleaved burst order. tdo jtag serial output synchronous serial data out to the jtag circuit . delivers data on the negative edge of tck. tdi jtag serial input synchronous serial data in to the jtag circuit . sampled on the rising edge of tck. [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 8 of 29 functional overview the CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 are synchronous-pipelined burst nobl srams designed specifically to eliminate wait states during read or write transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 3.0 ns (250-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edg e of the clock. if cen is active low and adv/ld is asserted low, the address presented to the device is latched. the access can either be a read or write operation, depend ing on the status of the write enable (we ). bw [x] can be used to conduct byte write operations. write operations are qualif ied by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and de selects) are pipelined. adv/ld must be driven low after the dev ice is deselected to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low to drive out the requested data. during the second clock, a subsequent operation (read, write, or deselect) can be initiated. deselecting the device is also pipelined. therefore, when the sr am is deselected at clock rise by one of the chip enable signals, its output tri-states following the next clock rise. burst read accesses the CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 have an on-chip burst counter t hat enables the user to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low to load a new address into the sram, as described in the single read accesses section. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and wraps around when incremented sufficiently. a high input on adv/ld increments the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write accesses are initiated w hen the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the signal we is asserted low. the address presented to the address inputs is loaded into the address register . the write signals are latched into the control logic block. on the subsequent clock rise t he data lines are automatically tri-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dq and dqp (dq a,b,c,d /dqp a,b,c,d for CY7C1470BV25, dq a,b /dqp a,b for cy7c1472bv25, and dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for cy7c1474bv25). in addition, the address for the subsequent tms test mode select synchronous tms pin controls the test access port state machine . sampled on the rising edge of tck. tck jtag clock clock input to th e jtag circuitry . v dd power supply power supply inputs to the core of the device . v ddq io power supply power supply for the io circuitry . v ss ground ground for the device . must be connected to ground of the system. nc ? no connects . this pin is not connected to the die. nc(144m, 288m, 576m, 1g) ? these pins are not connected . they are used for expansion to the 144m, 288m, 576m, and 1g densities. zz input- asynchronous zz ?sleep? input . this active high input places the device in a non-time critical ?sleep? condition with data integrity preserved. for normal operation, this pin has must be low or left floating. zz pin has an internal pull down. pin definitions (continued) pin name io type pin description [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 9 of 29 access (read, write, or desele ct) is latched into the address register (provided the appropriat e control signals are asserted). on the next clock rise the data presented to dq and dqp (dq a,b,c,d /dqp a,b,c,d for CY7C1470BV25, dq a,b /dqp a,b for cy7c1472bv25, dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for cy7c1474bv25) (or a subset for byte write operations, see partial write cycle description on page 11 for details) inputs is latched into the device and the write is complete. the data written during the writ e operation is controlled by bw (bw a,b,c,d for CY7C1470BV25, bw a,b for cy7c1472bv25, and bw a,b,c,d,e,f,g,h for cy7c1474bv25) signals. the CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 provides byte write capab ility that is described in partial write cycle description on page 11 . asserting the we input with the selected bw input selectively writes to only the desired bytes. bytes not selected during a byte write operation remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write o perations. byte write capability has been included to greatly simplify read, modify, or write sequences, which can be reduced to simple byte write operations. because the CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 are common io devices, data must not be driven into the device while the outputs are active. oe can be deasserted high before presenting data to the dq and dqp (dq a,b,c,d /dqp a,b,c,d for CY7C1470BV25, dq a,b /dqp a,b for cy7c1472bv25, and dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for cy7c1474bv25) inputs. doing so tri-states the output drivers. as a safety precaution, dq and dqp (dq a,b,c,d /dqp a,b,c,d for CY7C1470BV25, dq a,b /dqp a,b for cy7c1472bv25, and dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for cy7c1474bv25) are automatically tri-stated during th e data portion of a write cycle, regardless of the state of oe . burst write accesses the CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 has an on-chip burst counter that enables the user to supply a single address and conduct up to four write op erations without reasserting the address inputs. adv/ld must be driven low to load the initial address, as described in single write accesses on page 8 . when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw (bw a,b,c,d for CY7C1470BV25, bw a,b for cy7c1472bv25, and bw a,b,c,d,e,f,g,h for cy7c1474bv25) inputs must be driven in each cycle of the burst write to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data inte grity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected before entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. linear burst address table (mode = gnd) first address second address third address fourth address a1, a0 a1, a0 a1, a0 a1, a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 interleaved burst address table (mode = floating or v dd ) first address second address third address fourth address a1, a0 a1, a0 a1, a0 a1, a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz ? v dd ?? 0.2 v ? 120 ma t zzs device operation to zz zz ??? v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz ? 0.2 v 2t cyc ?ns t zzi zz active to sleep current this parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep curr ent this parameter is sampled 0 ? ns [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 10 of 29 truth table the truth table for CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 follows. [1, 2, 3, 4, 5, 6, 7] operation address used ce zz adv/ld we bw x oe cen clk dq deselect cycle none h l l x x x l l-h tri-state continue deselect cycle none x l h x x x l l-h tri-state read cycle (begin burst) external l l l h x l l l-h data out (q) read cycle (continue burst) next x l h x x l l l-h data out (q) nop/dummy read (begin burst) external l l l h x h l l-h tri-state dummy read (continue burst) next x l h x x h l l-h tri-state write cycle (begin burst) external l l l l l x l l-h data in (d) write cycle (continue burst) next x l h x l x l l-h data in (d) nop/write abort (begin burst) none l l l l h x l l-h tri-state write abort (continue burst) next x l h x h x l l-h tri-state ignore clock edge (stall) current x l x x x x h l-h ? sleep mode none x h x x x x x x tri-state notes 1. x = ?don't care?, h = logic high, l = logic low, ce stands for all chip enables active. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see partial write cycle description on page 11 for details. 2. write is defined by we and bw [a:d] . see partial write cycle description on page 11 for details. 3. when a write cycle is detected, all ios are tri-stated, even during byte writes. 4. the dq and dqp pins are controlled by the current cycle and the oe signal. 5. cen = h inserts wait states. 6. device powers up deselected with the ios in a tri-state condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during wr ite cycles.during a read cycle dq s and dqp [a:d] = tri-state when oe is inactive or when the device is deselected, and dq s = data when oe is active. [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 11 of 29 partial write cycle description the partial write cycle description for CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 follows. [8, 9, 10, 11] function (CY7C1470BV25) we bw d bw c bw b bw a read h x x x x write ? no bytes written l h h h h write byte a ? (dq a and dqp a )lhhhl write byte b ? (dq b and dqp b )lhhlh write bytes b, a l h h l l write byte c ? (dq c and dqp c )lhlhh write bytes c, a l h l h l write bytes c, b l h ll l h write bytes c, b, a l h l l l write byte d ? (dq d and dqp d )llhhh write bytes d, a l l h h l write bytes d, b l l h l h write bytes d, b, a l l h l l write bytes d, c l l l h h write bytes d, c, a l l l h l write bytes d, c, b l l l l h write all bytes l l l l l function (cy7c1472bv25) we bw b bw a read h x x write ? no bytes written l h h write byte a ? (dq a and dqp a )lhl write byte b ? (dq b and dqp b )llh write both bytes l l l function (cy7c1474bv25) we bw x read h x write ? no bytes written l h write byte x ??? (dq x and dqp x) ll write all bytes l all bw = l notes 8. x = ?don't care?, h = logic high, l = logic low, ce stands for all chip enables active. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see partial write cycle description for details. 9. write is defined by we and bw [a:d] . see partial write cycle description for details. 10. when a write cycle is detected, all ios are tri-stated, even during byte writes. 11. table lists only a partial listing of the byte write combinations. any combination of bw [a:d] is valid. appropriate write is based on which byte write is active. [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 12 of 29 ieee 1149.1 serial boundary scan (jtag) the CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram . note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 2.5 v io logic levels. the CY7C1470BV25, cy7c1472bv25, and cy7c1474bv25 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull up resistor. tdo must be left unconnected. duri ng power up, the device comes up in a reset state, which does not interfere with the operation of the device. the 0/1 next to each state represents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially in put information into the registers and can be connected to the inpu t of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information about loading the instruction register, see the tap controller state diagram . tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see tap controller block diagram .) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram .) performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. during power up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo balls to scan the data in and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. tap controller state diagram test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 tap controller block diagra bypass register 0 instruction register 0 1 2 identication register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry tck tms tap controller tdi tdo selection circuitry [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 13 of 29 instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram on page 12 . during power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is pl aced in a reset state as described in the previous section. when the tap controller is in t he capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to enable fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this shifts the data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is lo aded with the contents of the ram io ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z in structions can be used to capture the contents of the io ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the re gister is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr stat e when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regi ster has a vendor code and other information described in identification register definitions on page 16 . tap instruction set overview eight different instructions are possible with the three-bit instruction register. all co mbinations are listed in identification codes on page 17 . three of these instructions are listed as reserved and must not be used. the other five instructions are described in this section in detail. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the io buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a capture of the io ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction after it is shift ed in, the tap controller must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is executed whenever the instruction register is loaded with all 0s. extest is not implemented in this sr am tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. ther e is one difference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high z state. idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction register. it also places the instruction register between the tdi and tdo balls and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is load ed into the instruction register during power up or whenever the tap controller is in a test logic reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high z state. sample/preload sample/preload is a 1149.1 m andatory instruction. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output may undergo a transition. the tap may then tr y to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time (t cs plus t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if th is is an issue, it is still [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 14 of 29 possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction has the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 15 of 29 tap ac switchi ng characteristics over the operating range [12, 13] parameter description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns notes 12. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 13. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 16 of 29 2.5 v tap ac test conditions input pulse levels................................................v ss to 2.5 v input rise and fall time .....................................................1 ns input timing reference levels...... .................................. 1.25 v output reference levels ............................................... 1.25 v test load termination supply voltage ........................... 1.25 v note 14. all voltages refer to v ss (gnd). 2.5 v tap ac output load equivalent tdo 1.25v 20pf z = 50 o 50 (0 c < t a < +70 c; v dd = 2.5 v 0.125 v unless otherwise noted) [14] parameter description test conditions min max unit v oh1 output high voltage i oh = ?1.0 ma, v ddq = 2.5 v 1.7 ? v v oh2 output high voltage i oh = ?100 ? a, v ddq = 2.5 v 2.1 ? v v ol1 output low voltage i ol = 1.0 ma, v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 ? a, v ddq = 2.5 v ? 0.2 v v ih input high voltage v ddq = 2.5 v 1.7 v dd + 0.3 v v il input low voltage v ddq = 2.5 v ?0.3 0.7 v i x input load current gnd ? v i ? v ddq ?5 5 ? a identification regi ster definitions instruction field CY7C1470BV25 (2 m 36) cy7c1472bv25 (4 m 18) cy7c1474bv25 (1 m 72) description revision number (31:29) 000 000 000 describes the version number device depth (28:24) 01011 01011 01011 reserved for internal use architecture/memory type (23:18) 001000 001000 001000 defines memory type and architecture bus width/density (17:12) 100100 010100 110100 defines width and density cypress jedec id code (11:1) 00000110100 000001 10100 00000110100 allows unique identification of sram vendor id register presence indicator (0 ) 1 1 1 indicates the presence of an id register scan register sizes register name bit size ( 36) bit size ( 18) bit size ( 72) instruction 3 3 3 bypass 1 1 1 id 32 32 32 boundary scan order?165-ball fbga 71 52 ? boundary scan order?209-ball bga ? ? 110 [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 17 of 29 identification codes instruction code description extest 000 captures io ring contents. places th e boundary scan register between tdi and tdo. forces all sram outputs to high z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures io ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instru ction is reserved for future use. sample/preload 100 captures io ring contents. places the boundary sc an register between tdi and tdo. does not affect sram operation. this instructio n does not implement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use: this instru ction is reserved for future use. reserved 110 do not use: this instru ction is reserved for future use. bypass 111 places the bypass register between tdi and td o. this operation does not affect sram operations. boundary scan exit order (2 m 36) bit # 165-ball id bit # 165-ball id bit # 165-ball id bit # 165-ball id 1c121r341j1161b7 2 d1 22 p2 42 k10 62 b6 3 e1 23 r4 43 j10 63 a6 4d2 24p6 44h11 64b5 5e2 25r6 45g11 65a5 6f1 26r8 46f11 66a4 7g1 27p3 47e11 67b4 8 f2 28 p4 48 d10 68 b3 9g2 29p8 49d11 69a3 10 j1 30 p9 50 c11 70 a2 11 k1 31 p10 51 g10 71 b2 12 l1 32 r9 52 f10 13 j2 33 r10 53 e10 14 m1 34 r11 54 a9 15 n1 35 n11 55 b9 16 k2 36 m11 56 a10 17 l2 37 l11 57 b10 18 m2 38 m10 58 a8 19 r1 39 l10 59 b8 20 r2 40 k11 60 a7 [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 18 of 29 boundary scan exit order (4 m 18) bit # 165-ball id bit # 165-ball id bit # 165-ball id bit # 165-ball id 1d214r427l1040b10 2e215p628k1041a8 3 f2 16 r6 29 j10 42 b8 4g2 17r8 30h11 43a7 5j1 18p3 31g11 44b7 6k119p432f1145b6 7l1 20p8 33e11 46a6 8m1 21p9 34d11 47b5 9 n1 22 p10 35 c11 48 a4 10 r1 23 r9 36 a11 49 b3 11 r2 24 r10 37 a9 50 a3 12 r3 25 r11 38 b9 51 a2 13 p2 26 m10 39 a10 52 b2 boundary scan exit order (1 m 72) bit # 209-ball id bit # 209-ball id bit # 209-ball id bit # 209-ball id 1 a1 29 t1 57 u10 85 b11 2a2 30t2 58t11 86b10 3b1 31u1 59t10 87a11 4b2 32u2 60r11 88a10 5 c1 33 v1 61 r10 89 a7 6c2 34v2 62p11 90a5 7 d1 35 w1 63 p10 91 a9 8d2 36w2 64n11 92u8 9 e1 37 t6 65 n10 93 a6 10 e2 38 v3 66 m11 94 d6 11 f1 39 v4 67 m10 95 k6 12 f2 40 u4 68 l11 96 b6 13 g1 41 w5 69 l10 97 k3 14 g2 42 v6 70 p6 98 a8 15 h1 43 w6 71 j11 99 b4 16 h2 44 v5 72 j10 100 b3 17 j1 45 u5 73 h11 101 c3 18 j2 46 u6 74 h10 102 c4 19 l1 47 w7 75 g11 103 c8 20 l2 48 v7 76 g10 104 c9 21 m1 49 u7 77 f11 105 b9 22 m2 50 v8 78 f10 106 b8 23 n1 51 v9 79 e10 107 a4 24 n2 52 w11 80 e11 108 c6 25 p1 53 w10 81 d11 109 b7 26 p2 54 v11 82 d10 110 a3 27 r2 55 v10 83 c11 28 r1 56 u11 84 c10 [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 19 of 29 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................. ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd ......?0.5 v to +3.6 v supply voltage on v ddq relative to gnd ..... ?0.5 v to +v dd dc to outputs in tri-state..................?0.5 v to v ddq + 0.5 v dc input voltage ................................. ?0.5 v to v dd + 0.5 v current into outputs (low)..... .................................... 20 ma static discharge voltage......................................... > 2001 v (mil-std-883, method 3015) latch up current.................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 2.5 v ? 5% / +5% 2.5 v ? 5% to v dd industrial ?40 c to +85 c electrical characteristics over the operating range [15, 16] parameter description test conditions min max unit v dd power supply voltage 2.375 2.625 v v ddq io supply voltage for 2.5 v io 2.375 v dd v v oh output high voltage for 2.5 v io, i oh = ?? 1.0 ma 2.0 ? v v ol output low voltage for 2.5 v io, i ol = ? 1.0 ma ? 0.4 v v ih input high voltage [15] for 2.5 v io 1.7 v dd + 0.3 v v v il input low voltage [15] for 2.5 v io ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd ? 5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ? 30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 ? a i dd [17] v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz ? 450 ma ? 450 ma 5.0-ns cycle, 200 mhz 6.0-ns cycle, 167 mhz ? 400 ma i sb1 automatic ce power down current?ttl inputs max. v dd , device deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc 4.0-ns cycle, 250mhz ? 200 ma 5.0-ns cycle, 200 mhz ? 200 ma 6.0-ns cycle, 167 mhz ? 200 ma i sb2 automatic ce power down current?cmos inputs max. v dd , device deselected, v in ? 0.3 v or v in > v ddq ?? 0.3 v, f = 0 all speed grades ? 120 ma notes 15. overshoot: v ih (ac) < v dd +1.5 v (pulse width less than t cyc /2). undershoot: v il (ac) > ?2 v (pulse width less than t cyc /2). 16. t power-up : assumes a linear ramp from 0 v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . 17. the operation current is calculated with 50% read cycle and 50% write cycle. [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 20 of 29 i sb3 automatic ce power down current?cmos inputs max. v dd , device deselected, v in ? 0.3 v or v in > v ddq ?? 0.3 v, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz ? 200 ma 5.0-ns cycle, 200 mhz ? 200 ma 6.0-ns cycle, 167 mhz ? 200 ma i sb4 automatic ce power down current?ttl inputs max. v dd , device deselected, v in ? v ih or v in ? v il , f = 0 all speed grades ? 135 ma electrical characteristics (continued) over the operating range [15, 16] (continued) parameter description test conditions min max unit capacitance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions 100-pin tqfp max 165-ball fbga max 209-ball fbga max unit c address address input capacitance t a = 25 c, f = 1 mhz, v dd = 2.5 v v ddq = 2.5 v 6 6 6 pf c data data input capacitance 5 5 5 pf c ctrl control input capacitance 8 8 8 pf c clk clock input capacitance 6 6 6 pf c io input/output capacitance 5 5 5 pf thermal resistance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions 100-pin tqfp package 165-ball fbga package 209-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 24.63 16.3 15.2 ? c/w ? jc thermal resistance (junction to case) 2.28 2.1 1.7 ? c/w ac test loads and waveforms output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 2.5 v io test load [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 21 of 29 switching characteristics over the operating range [18, 19] parameter description 250 mhz 200 mhz 167 mhz unit min max min max min max t power [20] v cc (typical) to the first access read or write 1 ? 1 ? 1 ? ms clock t cyc clock cycle time 4.0 ? 5.0 ? 6.0 ? ns f max maximum operating frequency ? 250 ? 200 ? 167 mhz t ch clock high 2.0 ? 2.0 ? 2.2 ? ns t cl clock low 2.0 ? 2.0 ? 2.2 ? ns output times t co data output valid after clk rise ? 3.0 ? 3.0 ? 3.4 ns t oev oe low to output valid ? 3.0 ? 3.0 ? 3.4 ns t doh data output hold after clk rise 1.3 ? 1.3 ? 1.5 ? ns t chz clock to high z [21, 22, 23] ?3.0 ? 3.0 ? 3.4 ns t clz clock to low z [21, 22, 23] 1.3 ? 1.3 ? 1.5 ? ns t eohz oe high to output high z [21, 22, 23] ?3.0 ? 3.0 ? 3.4 ns t eolz oe low to output low z [21, 22, 23] 0? 0 ? 0 ? ns setup times t as address setup before clk rise 1.4 ? 1.4 ? 1.5 ? ns t ds data input setup before clk rise 1.4 ? 1.4 ? 1.5 ? ns t cens cen setup before clk rise 1.4 ? 1.4 ? 1.5 ? ns t wes we , bw x setup before clk rise 1.4 ? 1.4 ? 1.5 ? ns t als adv/ld setup before clk rise 1.4 ? 1.4 ? 1.5 ? ns t ces chip select setup 1.4 ? 1.4 ? 1.5 ? ns hold times t ah address hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns t dh data input hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns t cenh cen hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns t weh we , bw x hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns t alh adv/ld hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns t ceh chip select hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns notes 18. timing reference is 1.25 v when v ddq = 2.5 v. 19. test conditions shown in (a) of ac test loads and waveforms on page 20 unless otherwise noted. 20. this part has a voltage regulator internally; t power is the time power is supplied above v dd minimum initially, before a read or write operation can be initiated. 21. t chz , t clz , t eolz , and t eohz are specified with ac test conditions shown in (b) of ac test loads and waveforms on page 20 . transition is measured 200 mv from steady-state voltage. 22. at any supplied voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention betwee n srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user condi tions. device is designed to achieve high z before low z under the same system conditions. 23. this parameter is sampled and not 100% tested. [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 22 of 29 switching waveforms figure 2 shows read-write timing waveform. [24, 25, 26] figure 2. read/write timing write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds data i n-out (dq) t clz d(a1) d(a2) d(a5) q(a4) q(a3) d(a2+1) t doh t chz t co write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz t doh dont care undefined q(a6) q(a4+1) notes 24. for this waveform zz is tied low. 25. when ce is low, ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high,ce 1 is high, ce 2 is low, or ce 3 is high. 26. order of the burst sequence is determined by the status of the mode (0 = linear, 1 = interleaved).burst operations are optio nal. [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 23 of 29 figure 3 shows nop, stall and deselect cycles waveform. [27, 28, 29] figure 3. nop, stall and deselect cycles figure 4 shows zz mode timing waveform. [30, 31] figure 4. zz mode timing switching waveforms (continued) read q(a3) 456 78910 clk ce we cen bwx adv/ld address a3 a4 a5 d(a4) data in-out (dq) a1 q(a5) write d(a4) stall write d(a1) 123 read q(a2) stall nop read q(a5) deselect continue deselect dont care undefined t chz a2 d(a1) q(a2) q(a3) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 27. for this waveform zz is tied low. 28. when ce is low, ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high,ce 1 is high, ce 2 is low, or ce 3 is high. 29. the ignore clock edge or sta ll cycle (clock 3) illustrated cen being used to create a pause. a write is not performed during this cycle. 30. device must be deselected when entering zz mode. see truth table on page 10 for all possible signal conditions to deselect the device. 31. ios are in high z when exiting zz sleep mode. [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 24 of 29 ordering code definitions ordering information cypress offers other versions of this type of product in many different configurations and features. the below table contains o nly the list of parts that are currently available. for a complete listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution centers, manufacturer?s re presentatives and distributors. to find the office closest to you, visit us at t http://www.cypress.com/ go/datasheet/offices . speed (mhz) ordering code package diagram part and package type operating range 167 CY7C1470BV25-167axc 51-85050 100- pin thin quad flat pack (14 20 1.4 mm) pb-free commercial CY7C1470BV25-167bzxi 51-85165 165-ball fine-pitch ball grid array (15 17 1.4 mm) pb-free industrial 200 CY7C1470BV25-200axc 51-85050 100- pin thin quad flat pack (14 20 1.4 mm) pb-free commercial cy7c1472bv25-200axc CY7C1470BV25-200bzxc 51-85165 165-ball fine-pitch ball grid array (15 17 1.4 mm) pb-free commercial CY7C1470BV25-200bzxi industrial 250 CY7C1470BV25-250axc 51-85050 100- pin thin quad flat pack (14 20 1.4 mm) pb-free commercial x = t or blank t = tape and reel; blank = tube temperature range: x = c or i c = commercial; i = industrial package type: ax = 100-pin tqfp (pb-free) bzx = 165-ball fbga (pb-free) frequency range: xxx = 167 mhz or 200 mhz or 250 mhz v dd = 2.5 v process technology 147x = 1470 or 1472 or 1474 1470 = pl, 2mb x 36 (72mb) 1472 = pl, 4mb x 18 (72mb) 1474 = pl, 1mb x 72 (72mb) marketing code: 7c = srams company id: cy = cypress 7c 147x v25 - x xx b xxx cy x [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 25 of 29 package diagrams figure 5. 100-pin tqfp (14 20 1.4 mm), 51-85050 51-85050 *d [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 26 of 29 figure 6. 165-ball fbga (15 17 1.4 mm), 51-85165 package diagrams (continued) 51-85165 *b [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 27 of 29 acronyms document conventions units of measure acronym description bga ball grid array cmos complementary metal oxide semiconductor fbga fine-pitch ball grid array i/o input/output jtag joint test action group lsb least significant bit msb most significant bit oe output enable sram static random access memory tap test access port tck test clock tdi test data-in tdo test data-out tms test mode select tqfp thin quad flat pack ttl transistor transistor logic we write enable symbol unit of measure c degree celcius a micro amperes ma milli amperes mm milli meter ms milli seconds mhz mega hertz ns nano seconds ? ohms % percent pf pico farad vvolts wwatts [+] feedback
CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 document number: 001-15032 rev. *i page 28 of 29 document history page document title: CY7C1470BV25/cy7c1472bv25/cy7c1474bv25, 72 -mbit (2 m 36/4 m 18/1 m 72) pipelined sram with nobl? architecture document number: 001-15032 rev. ecn no. issue date orig. of change description of change ** 1032642 see ecn vkn/kkvtmp new data sheet *a 1562503 see ecn vkn/aesa removed 1.8v io offering from the data sheet *b 1897447 see ecn vkn/aesa added footnote 14 related to idd *c 2082487 see ecn vkn converted from preliminary to final *d 2159486 see ecn vkn/pyrs minor change-moved to the external web *e 2898663 03/24/2010 njy removed inactive parts from ordering information table; updated package diagram. *f 2905460 04/06/2010 vkn removed inactive part numbers CY7C1470BV25-167bzc,CY7C1470BV25-167bzi, CY7C1470BV25-167bzxc,CY7C1470BV25-200bzc, cy7c1472bv25-250bzc,cy7c1474bv25-167bgc, cy7c1474bv25-167bgi, cy7c1474bv25-200bgc,cy7c1474bv25-200bgi, cy7c1474bv25-200bgxi,from the ordering information table. *g 3061663 10/15/2010 njy removed pruned parts cy 7c1472bv25-200bzi, cy7c1472bv25-200bzit from ordering information table. removed associated package. added ordering code definitions, sales links, and toc. *h 3207526 03/28/2011 njy updated ordering information . updated package diagrams . updated in new template. *i 3257192 05/14/2011 njy updated ordering information . added acronyms and units of measure . [+] feedback
document number: 001-15032 rev. *i revised may 17, 2011 page 29 of 29 nobl and no bus latency are trademarks of cypress semiconductor corporation. zbt is a trademark of integrated device technology , inc. all products and company names mentioned in this document may be the trademarks of their respective holders. CY7C1470BV25 cy7c1472bv25, cy7c1474bv25 ? cypress semiconductor corporation, 2007-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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